1. Technical Field
The present invention relates to memory devices in general, and in particular to embedded dynamic random access memory devices. Still more particularly, the present invention relates to a method and apparatus for allocating data usages within an embedded dynamic random access memory device.
2. Description of the Prior Art
Embedded dynamic random access memory (DRAM) is a type of integrated circuit having both memory cells and their control circuits formed on a single semiconductor chip. Specifically, a complete embedded DRAM includes multiple transfer field effect transistors (FETs), a capacitor coupled to each of the transfer FETs, and a group of control circuitry. Each transfer FET acts as a switch between the lower electrode of the capacitor and a bit line. As such, data within the capacitor can be written in or read out from the embedded DRAM.
Embedded DRAMs are capable of transferring a large quantity of data at a very high speed. Because of their relatively high processing speed and storage capacity, embedded DRAMs have been commonly employed in various high-end integrated circuits, such as graphic processors. In addition, embedded DRAMs can provide an embedded processor a faster access to a relatively large capacity of on-chip memory at a lower cost than that currently available using conventional embedded static random access memories (SRAMs) and/or electrically erasable programmable read only memories (EEPROMs).
The present disclosure provides a method for allocating data usages within an embedded DRAM.
In accordance with a preferred embodiment of the present invention, an apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.